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FEATURES

LTM4601HV 12A 28VIN DC/DC Module with PLL, Output Tracking and Margining DESCRIPTIO
The LTM(R)4601HV is a complete 12A step-down switch mode DC/DC power supply with onboard switching controller, MOSFETs, inductor and all support components. The Module is housed in a small surface mount 15mm x15mm x 2.8mm LGA package. Operating over an input voltage range of 4.5 to 28V, the LTM4601HV supports an output voltage range of 0.6V to 5V as well as output voltage tracking and margining. The high efficiency design delivers 12A continuous current (14A peak). Only bulk input and output capacitors are needed to complete the design. The low profile (2.8mm) and light weight (1.7g) package easily mounts in unused space on the back side of PC boards for high density point of load regulation. The Module can be synchronized with an external clock for reducing undesirable frequency harmonics and allows PolyPhase(R) operation for high load currents. A high switching frequency and adaptive on-time current mode architecture deliver a very fast transient response to line and load changes without sacrificing stability. An onboard differential remote sense amplifier can be used to accurately regulate an output voltage independent of load current.
, LT, LTC, LTM and PolyPhase are registered trademarks of Linear Technology Corporation. Module is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5847554, 6580258, 6304066, 6476589, 6774611, 6677210
Complete Switch Mode Power Supply Wide Input Voltage Range: 4.5V to 28V 12A DC Typical, 14A Peak Output Current 0.6V to 5V Output Voltage Output Voltage Tracking and Margining Parallel Multiple ModulesTM for Current Sharing Differential Remote Sensing for Precision Regulation PLL Frequency Synchronization 1.5% Regulation Current Foldback Protection (Disabled at Start-Up) Pb-Free (e4) RoHS Compliant Package with Gold Finish Pads Ultrafast Transient Response Current Mode Control Up to 95% Efficiency at 5VIN, 3.3VOUT Programmable Soft-Start Output Overvoltage Protection Small Footprint, Low Profile (15mm x 15mm x 2.8mm) Surface Mount LGA Package
APPLICATIO S

Telecom and Networking Equipment Servers Industrial Equipment Point of Load Regulation
TYPICAL APPLICATIO
VIN 4.5V TO 28V VIN PGOOD RUN COMP INTVCC DRVCC MPGM SGND
2.5V/12A Power Supply with 4.5V to 28V Input
CLOCK SYNC TRACK/SS CONTROL PLLIN TRACK/SS VOUT VFB MARG0 MARG1 VOUT_LCL DIFFVOUT VOSNS+ VOSNS- fSET RSET 19.1k
4601HV TA01a
Efficiency and Power Loss vs Load Current
95 90 85 EFFICIENCY (%) 12VIN 5 24VIN POWER LOSS (W) EFFICIENCY 4 3 24VIN 12VIN POWER LOSS 1 0 0 2 8 6 4 10 LOAD CURRENT (A) 12 14 2 6
100pF MARGIN CONTROL
VOUT 2.5V 12A
80 75 70 65 60 55 50 45
ON/OFF CIN
LTM4601HV
COUT
R1 392k 5% MARGIN
PGND
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4601HV TA01b
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LTM4601HV ABSOLUTE
(Note 1)
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
INTVCC PLLIN TRACK/SS RUN COMP MPGM TOP VIEW
INTVCC, DRVCC, VOUT_LCL, VOUT (VOUT 3.3V with Remote Sense Amp) .................................... -0.3V to 6V PLLIN, TRACK/SS, MPGM, MARG0, MARG1, PGOOD, fSET .............................. -0.3V to INTVCC + 0.3V RUN ............................................................. -0.3V to 5V VFB, COMP ................................................ -0.3V to 2.7V VIN ............................................................. -0.3V to 28V VOSNS+, VOSNS- ............................. -0.3V to INTVCC - 1V Operating Temperature Range (Note 2) ... -40C to 85C Junction Temperature ........................................... 125C Storage Temperature Range................... -55C to 125C
VIN
PGND
VOUT
fSET MARG0 MARG1 DRVCC VFB PGOOD SGND VOSNS+ DIFFVOUT VOUT_LCL VOSNS-
LGA PACKAGE 118-LEAD (15mm 15mm 2.8mm) TJMAX = 125C, JA = 15C/W, JC = 6C/W, JA DERIVED FROM 95mm x 76mm PCB WITH 4 LAYERS WEIGHT = 1.7g
ORDER PART NUMBER LTM4601HVEV#PBF LTM4601HVIV#PBF
LGA PART MARKING* LTM4601HVV LTM4601HVV
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
ELECTRICAL CHARACTERISTICS
SYMBOL VIN(DC) VOUT(DC) Input Specifications VIN(UVLO) IINRUSH(VIN) Undervoltage Lockout Threshold Input Inrush Current at Startup PARAMETER Input DC Voltage Output Voltage (With Remote Sense Amp)
The denotes the specifications which apply over the -40C to 85C temperature range, otherwise specifications are at TA = 25C, VIN = 12V. Per typical application (front page) configuration.
CONDITIONS
MIN 4.5 1.478
TYP
MAX 28
UNITS V V V A A mA mA mA mA A A A A
CIN = 10F x3, COUT = 200F VIN = 12V, VOUT = 1.5V, IOUT = 0 IOUT = 0A IOUT = 0A. VOUT = 1.5V VIN = 5V VIN = 12V VIN = 12V, VOUT = 1.5V, No Switching VIN = 12V, VOUT = 1.5V, Switching Continuous VIN = 5V, VOUT = 1.5V, No Switching VIN = 5V, VOUT = 1.5V, Switching Continuous Shutdown, RUN = 0, VIN = 12V VIN = 12V, VOUT = 1.5V, IOUT = 12A VIN = 12V, VOUT = 3.3V, IOUT = 12A VIN = 5V, VOUT = 1.5V, IOUT = 12A No Load
1.5 3.2 0.6 0.7 3.8 38 2.5 42 22 1.81 3.63 4.29
1.522 4
IQ(VIN,NO LOAD)
Input Supply Bias Current
IS(VIN)
Input Supply Current
INTVCC
VIN = 12V, RUN > 2V
4.7
5
5.3
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LTM4601HV ELECTRICAL CHARACTERISTICS
SYMBOL IOUTDC VOUT(LINE) VOUT VOUT(0-12A) VOUT VOUT(AC) PARAMETER Output Specifications Output Continuous Current Range VIN = 12V, VOUT = 1.5V (See Output Current Derating Curves for Different VIN, VOUT and TA) Line Regulation Accuracy Load Regulation Accuracy VOUT = 1.5V, IOUT = 0A, VIN = 4.5V - 28V VOUT = 1.5V, IOUT = 0A to 12A, with RSA VIN = 5V VIN = 12V IOUT = 0A, COUT = 2x, 100F/X5R/Ceramic VIN = 12V, VOUT = 1.5V VIN = 5V, VOUT = 1.5V IOUT = 5A, VIN = 12V, VOUT = 1.5V COUT = 200F, VOUT = 1.5V, IOUT = 0A VIN = 12V VIN = 5V COUT = 200F, VOUT = 1.5V, IOUT = 1A Resisitive Load VIN = 12V VIN = 5V Load: 0% to 50% to 0% of Full Load, COUT = 2 x 22F/Ceramic, 470F, 4V Sanyo POSCAP VIN = 12V VIN = 5V
The denotes the specifications which apply over the -40C to 85C temperature range, otherwise specifications are at TA = 25C, VIN = 12V. Per typical application (front page) configuration.
CONDITIONS MIN 0 TYP MAX 12 UNITS A
0.3
%

0.25 0.25 20 18 850 20 20
% % mVP-P mVP-P kHz mV mV
Output Ripple Voltage
fS VOUT(START)
Output Ripple Voltage Frequency Turn-On Overshoot, TRACK/SS = 10nF Turn-On Time, TRACK/SS = Open
tSTART
0.5 0.7
ms ms
VOUTLS
Peak Deviation for Dynamic Load
35 35 25 17 17 0 0 1 3 2 INTVCC - 1 INTVCC 1.25
mV mV s A A V V mV V/V MHz V/s k dB 0.606 1.9 -2.0 100 V V A ns
tSETTLE IOUTPK
Settling Time for Dynamic Load Step Load: 0% to 50%, or 50% to 0% of Full Load VIN = 12V Output Current Limit COUT = 200F, Table 2 VIN = 12V, VOUT = 1.5V VIN = 5V, VOUT = 1.5V
Remote Sense Amp (Note 3) VOSNS+, VOSNS- CM Range DIFFVOUT Range VOS AV GBP SR RIN CMRR Control Stage VFB VRUN ISS/TRACK tON(MIN) Error Amplifier Input Voltage Accuracy RUN Pin On/Off Threshold Soft-Start Charging Current Minimum On Time VSS/TRACK = 0V (Note 4) IOUT = 0A, VOUT = 1.5V
Common Mode Input Voltage Range VIN = 12V, RUN > 2V Output Voltage Range Input Offset Voltage Magnitude Differential Gain Gain Bandwidth Product Slew Rate Input Resistance Common Mode Rejection Mode VOSNS+ to GND VIN = 12V, DIFF OUT Load = 100k
20 100 0.594 1 -1.0 0.6 1.5 -1.5 50
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LTM4601HV
The denotes the specifications which apply over the -40C to 85C temperature range, otherwise specifications are at TA = 25C, VIN = 12V. Per typical application (front page) configuration.
SYMBOL tOFF(MIN) RPLLIN IDRVCC RFBHI VMPGM VMARG0, VMARG1 PGOOD Output VFBH VFBL VFB(HYS) PGOOD Upper Threshold PGOOD Lower Threshold PGOOD Hysteresis VFB Rising VFB Falling VFB Returning 7 -7 10 -10 1.5 Note 2: The LTM4601HVE is guaranteed to meet performance specifications from 0C to 85C. Specifications over the -40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4601HVI is guaranteed and tested over the -40C to 85C temperature range. Note 3: Remote sense amplifier recommended for 3.3V output. Note 4: 100% tested at wafer level only. 13 -13 % % % PARAMETER Minimum Off Time PLLIN Input Resistance Current into DRVCC Pin Resistor Between VOUT and VFB Margin Reference Voltage MARG0, MARG1 Voltage Thresholds VOUT = 1.5V, IOUT = 1A, Frequency = 850kHz, DRVCC = 5V 60.098 CONDITIONS (Note 4) MIN TYP 250 50 18 60.4 1.18 1.4 25 60.702 MAX 400 UNITS ns k mA k V V
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.
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LTM4601HV TYPICAL PERFOR A CE CHARACTERISTICS (See Figures 19 and 20 for all curves)
Efficiency vs Load Current with 5VIN
100 95 90 EFFICIENCY (%) EFFICIENCY (%) 85 80 75 70 65 60 0 0.6VOUT 1.2VOUT 1.5VOUT 2.5VOUT 3.3VOUT 5 10 15
4601HV G01
80 75 70 65 60 55 50 0 0.6VOUT 1.2VOUT 1.5VOUT 2.5VOUT 3.3VOUT 5VOUT 10 5 LOAD CURRENT (A) 15
4601HV G02
EFFICIENCY (%)
LOAD CURRENT (A)
1.2V Transient Response
VOUT 50mV/DIV IOUT 5A/DIV VOUT 50mV/DIV
20s/DIV 1.2V AT 6A/s LOAD STEP COUT = 3 * 22F 6.3V CERAMICS 470F 4V SANYO POSCAP C3 = 100pF
2.5V Transient Response
VOUT 50mV/DIV VOUT 50mV/DIV
IOUT 5A/DIV
20s/DIV 2.5V AT 6A/s LOAD STEP COUT = 3 * 22F 6.3V CERAMICS 470F 4V SANYO POSCAP C3 = 100pF
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Efficiency vs Load Current with 12VIN
100 95 90 85 95 90 85 80 75 70 65 60 55 50 45
Efficiency vs Load Current with 24VIN
1.5VOUT 2.5VOUT 3.3VOUT 5.0VOUT 0 10 5 LOAD CURRENT (A) 15
4601HV G03
1.5V Transient Response
VOUT 50mV/DIV
1.8V Transient Response
IOUT 5A/DIV
IOUT 5A/DIV
4601HV G04
20s/DIV 1.5V AT 6A/s LOAD STEP COUT = 3 * 22F 6.3V CERAMICS 470F 4V SANYO POSCAP C3 = 100pF
4601HV G05
20s/DIV 1.8V AT 6A/s LOAD STEP COUT = 3 * 22F 6.3V CERAMICS 470F 4V SANYO POSCAP C3 = 100pF
4601HV G06
3.3V Transient Response
IOUT 5A/DIV
4601HV G07
20s/DIV 3.3V AT 6A/s LOAD STEP COUT = 3 * 22F 6.3V CERAMICS 470F 4V SANYO POSCAP C3 = 100pF
4601 G08
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LTM4601HV TYPICAL PERFOR A CE CHARACTERISTICS (See Figures 19 and 20 for all curves)
Start-Up, IOUT = 0A
VOUT 0.5V/DIV VOUT 0.5V/DIV IIN 1A/DIV
IIN 0.5A/DIV
5ms/DIV VIN = 12V VOUT = 1.5V COUT = 470F 3 x 22F SOFT-START = 10nF
VIN to VOUT Step-Down Ratio
5.5 5.0 4.5 OUTPUT VOLTAGE (V) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 2 4 6 8 10 12 14 16 18 20 22 24 INPUT VOLTAGE (V)
4601HV G11
Short-Circuit Protection, IOUT = 0A
VOUT 0.5V/DIV IIN 1A/DIV VOUT 0.5V/DIV IIN 1A/DIV
50s/DIV VIN = 12V VOUT = 1.5V COUT = 470F 3 x 22F SOFT-START = 10nF
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Start-Up, IOUT = 12A (Resistive Load)
4601HV G09
2ms/DIV VIN = 12V VOUT = 1.5V COUT = 470F 3 x 22F SOFT-START = 10nF
4601HV G10
Track, IOUT = 12A
3.3V OUTPUT WITH 130k FROM VOUT TO ION 5V OUTPUT WITH 100k RESISTOR ADDED FROM fSET TO GND 5V OUTPUT WITH NO RESISTOR ADDED FROM fSET TO GND 2.5V OUTPUT 1.8V OUTPUT 1.5V OUTPUT 1.2V OUTPUT TRACK/SS 0.5V/DIV VFB 0.5V/DIV VOUT 1V/DIV
2ms/DIV VIN = 12V VOUT = 1.5V COUT = 470F 3 x 22F SOFT-START = 10nF
4601HV G12
Short-Circuit Protection, IOUT = 12A
4601HV G13
50s/DIV VIN = 12V VOUT = 1.5V COUT = 470F 3 x 22F SOFT-START = 10nF
4601HV G14
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LTM4601HV PI FU CTIO S
VIN (Bank 1): Power Input Pins. Apply input voltage between these pins and PGND pins. Recommend placing input decoupling capacitance directly between VIN pins and PGND pins. VOUT (Bank 3): Power Output Pins. Apply output load between these pins and PGND pins. Recommend placing output decoupling capacitance directly between these pins and PGND pins. Review the figure below. PGND (Bank 2): Power ground pins for both input and output returns. VOSNS- (Pin M12): (-) Input to the Remote Sense Amplifier. This pin connects to the ground remote sense point. The remote sense amplifier is used for VOUT 3.3V. VOSNS+ (Pin J12): (+) Input to the Remote Sense Amplifier. This pin connects to the output remote sense point. The remote sense amplifier is used for VOUT 3.3V. DIFFVOUT (Pin K12): Output of the Remote Sense Amplifier. This pin connects to the VOUT_LCL pin. DRVCC (Pin E12): This pin normally connects to INTVCC for powering the internal MOSFET drivers. This pin can be biased up to 6V from an external supply with about 50mA capability, or an external circuit shown in Figure 18. This improves efficiency at the higher input voltages by reducing power dissipation in the module. INTVCC (Pin A7): This pin is for additional decoupling of the 5V internal regulator.
A VIN B BANK 1 C D E PGND F BANK 2 G H J VOUT K BANK 3 L M 1 2 3 4 5 6 7 8 9 10 11 12
INTVCC PLLIN TRACK/SS RUN COMP MPGM fSET MARG0 MARG1 DRVCC VFB PGOOD SGND VOSNS+ DIFFVOUT VOUT_LCL VOSNS-
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(See Package Description for Pin Assignment)
PLLIN (Pin A8): External Clock Synchronization Input to the Phase Detector. This pin is internally terminated to SGND with a 50k resistor. Apply a clock above 2V and below INTVCC. See Applications Information. TRACK/SS (Pin A9): Output Voltage Tracking and SoftStart Pin. When the module is configured as a master output, then a soft-start capacitor is placed on this pin to ground to control the master ramp rate. A soft-start capacitor can be used for soft-start turn on as a stand alone regulator. Slave operation is performed by putting a resistor divider from the master output to the ground, and connecting the center point of the divider to this pin. See Applications Information. MPGM (Pin A12): Programmable Margining Input. A resistor from this pin to ground sets a current that is equal to 1.18V/R. This current multiplied by 10k will equal a value in millivolts that is a percentage of the 0.6V reference voltage. See Applications Information. To parallel LTM4601HVs, each requires an individual MPGM resistor. Do not tie MPGM pins together. fSET (Pin B12): Frequency Set Internally to 850kHz. An external resistor can be placed from this pin to ground to increase frequency. This pin can be decoupled with a 1000pF capacitor. See Applications Information for frequency adjustment. VFB (Pin F12): The Negative Input of the Error Amplifier. Internally, this pin is connected to VOUT_LCL pin with a 60.4k precision resistor. Different output voltages can be programmed with an additional resistor between VFB and SGND pins. See Applications Information.
TOP VIEW
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LTM4601HV PI FU CTIO S
MARG0 (Pin C12): This pin is the LSB logic input for the margining function. Together with the MARG1 pin will determine if margin high, margin low or no margin state is applied. The pin has an internal pull-down resistor of 50k. See Applications Information. MARG1 (Pin D12): This pin is the MSB logic input for the margining function. Together with the MARG0 pin will determine if margin high, margin low or no margin state is applied. The pin has an internal pull-down resistor of 50k. See Applications Information. SGND (Pin H12): Signal Ground. This pin connects to PGND at output capacitor point. COMP (Pin A11): Current Control Threshold and Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. The voltage
SI PLIFIED BLOCK DIAGRA
VOUT_LCL >2V = ON <0.9V = OFF MAX = 5V
RUN 5.1V ZENER 60.4k INTERNAL COMP SGND POWER CONTROL Q1 1.5F
PGOOD COMP
MARG1 MARG0 VFB RSET 19.1k fSET 39.2k 50k 50k Q2 COUT PGND INTVCC 10k 10k 10k DIFFVOUT VOSNS- VOSNS+ 22F
MPGM TRACK/SS CSS
4.7F INTVCC DRVCC
50k
Figure 1. Simplified LTM4601HV Block Diagram
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+ -
PLLIN
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ranges from 0V to 2.4V with 0.7V corresponding to zero sense voltage (zero current). PGOOD (Pin G12): Output Voltage Power Good Indicator. Open-drain logic output that is pulled to ground when the output voltage is not within 10% of the regulation point, after a 25s power bad mask timer expires. RUN (Pin A10): Run Control Pin. A voltage above 1.9V will turn on the module, and when below 1.9V, will turn off the module. A programmable UVLO function can be accomplished with a resistor from VIN to this pin that is has a 5.1V zener to ground. Maximum pin voltage is 5V. Limit current into the RUN pin to less than 1mA. VOUT_LCL (Pin L12): VOUT connects directly to this pin to bypass the remote sense amplifier, or DIFFVOUT connects to this pin when remote sense amplifier is used.
VOUT 1M VIN 4.5V TO 28V CIN
+
VOUT 2.5V 12A
+
10k
4601HV F01
LTM4601HV DECOUPLI G REQUIRE E TS
SYMBOL CIN COUT PARAMETER External Input Capacitor Requirement (VIN = 4.5V to 28V, VOUT = 2.5V) External Output Capacitor Requirement (VIN = 4.5V to 28V, VOUT = 2.5V)
OPERATIO
Power Module Description The LTM4601HV is a standalone nonisolated switching mode DC/DC power supply. It can deliver up to 12A of DC output current with some external input and output capacitors. This module provides precisely regulated output voltage programmable via one external resistor from 0.6VDC to 5.0VDC over a 4.5V to 28V wide input voltage. The typical application schematics are shown in Figures 19 and 20. The LTM4601HV has an integrated constant on-time current mode regulator, ultralow RDS(ON) FETs with fast switching speed and integrated Schottky diodes. The typical switching frequency is 850kHz at full load. With current mode control and internal feedback loop compensation, the LTM4601HV module has sufficient stability margins and good transient performance under a wide range of operating conditions and with a wide range of output capacitors, even all ceramic output capacitors. Current mode control provides cycle-by-cycle fast current limit. Besides, foldback current limiting is provided in an overcurrent condition while VFB drops. Internal overvoltage and undervoltage comparators pull the open-drain PGOOD output low if the output feedback voltage exits a 10% window around the regulation point. Furthermore, in an
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TA = 25C, VIN = 12V. Use Figure 1 configuration.
MIN 20 100 TYP 30 200 MAX UNITS F F
CONDITIONS IOUT = 12A, 3x 10F Ceramics IOUT = 12A
overvoltage condition, internal top FET Q1 is turned off and bottom FET Q2 is turned on and held on until the overvoltage condition clears. Pulling the RUN pin below 1V forces the controller into its shutdown state, turning off both Q1 and Q2. At low load current, the module works in continuous current mode by default to achieve minimum output voltage ripple. When DRVCC pin is connected to INTVCC an integrated 5V linear regulator powers the internal gate drivers. If a 5V external bias supply is applied on the DRVCC pin, then an efficiency improvement will occur due to the reduced power loss in the internal linear regulator. This is especially true at the higher input voltage range. The LTM4601HV has a very accurate differential remote sense amplifier with very low offset. This provides for very accurate remote sense voltage measurement. The MPGM pin, MARG0 pin and MARG1 pin are used to support voltage margining, where the percentage of margin is programmed by the MPGM pin, and the MARG0 and MARG1 select margining. The PLLIN pin provides frequency synchronization of the device to an external clock. The TRACK/SS pin is used for power supply tracking and soft-start programming.
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LTM4601HV APPLICATIO S I FOR ATIO
The typical LTM4601HV application circuits are shown in Figures 19 and 20. External component selection is primarily determined by the maximum load current and output voltage. Refer to Table 2 for specific external capacitor requirements for a particular application. VIN to VOUT Step-Down Ratios There are restrictions in the maximum VIN and VOUT step down ratio that can be achieved for a given input voltage. These constraints are shown in the Typical Performance Characteristics curves labeled VIN to VOUT Step-Down Ratio. Note that additional thermal derating may apply. See the Thermal Considerations and Output Current Derating section of this data sheet. Output Voltage Programming and Margining The PWM controller has an internal 0.6V reference voltage. As shown in the Block Diagram, a 1M and a 60.4k 0.5% internal feedback resistor connects VOUT and VFB pins together. The VOUT_LCL pin is connected between the 1M and the 60.4k resistor. The 1M resistor is used to protect against an output overvoltage condition if the VOUT_LCL pin is not connected to the output, or if the remote sense amplifier output is not connected to VOUT_LCL. The output voltage will default to 0.6V. Adding a resistor RSET from the VFB pin to SGND pin programs the output voltage: VOUT = 0.6 V 60.4k + RSET RSET
Table 1. Standard 1% Resistor Values
RSET (k) VOUT (V) Open 0.6 60.4 1.2 40.2 1.5 30.1 1.8 25.5 2 19.1 2.5 13.3 3.3 8.25 5
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The MPGM pin programs a current that when multiplied by an internal 10k resistor sets up the 0.6V reference offset for margining. A 1.18V reference divided by the RPGM resistor on the MPGM pin programs the current. Calculate VOUT(MARGIN): VOUT(MARGIN) = %VOUT * VOUT 100 where %VOUT is the percentage of VOUT you want to margin, and VOUT(MARGIN) is the margin quantity in volts: RPGM = VOUT 1.18 V * * 10k 0.6 V VOUT(MARGIN) where RPGM is the resistor value to place on the MPGM pin to ground. The output margining will be margining of the value. This is controlled by the MARG0 and MARG1 pins. See the truth table below:
MARG0 LOW LOW HIGH HIGH MARG1 LOW HIGH LOW HIGH MODE NO MARGIN MARGIN UP MARGIN DOWN NO MARGIN
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Input Capacitors LTM4601HV module should be connected to a low AC impedance DC source. Input capacitors are required to be placed adjacent to the module. In Figure 18, the 10F ceramic input capacitors are selected for their ability to handle the large RMS current into the converter. An input bulk capacitor of 100F is optional. This 100F capacitor is only needed if the input source impedance is compromised by long inductive leads or traces.
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LTM4601HV APPLICATIO S I FOR ATIO
VOUT VIN For a buck converter, the switching duty-cycle can be estimated as: D=
Without considering the inductor current ripple, the RMS current of the input capacitor can be estimated as: ICIN(RMS) = IOUT(MAX ) % * D * ( 1- D )
In the above equation, % is the estimated efficiency of the power module. CIN can be a switcher-rated electrolytic aluminum capacitor, OS-CON capacitor or high volume ceramic capacitor. Note the capacitor ripple current ratings are often based on temperature and hours of life. This makes it advisable to properly derate the input capacitor, or choose a capacitor rated at a higher temperature than required. Always contact the capacitor manufacturer for derating requirements. In Figure 18, the 10F ceramic capacitors are together used as a high frequency input decoupling capacitor. In a typical 12A output application, three very low ESR, X5R or X7R, 10F ceramic capacitors are recommended. These decoupling capacitors should be placed directly adjacent to the module input pins in the PCB layout to minimize the trace inductance and high frequency AC noise. Each 10F ceramic is typically good for 2A to 3A of RMS ripple current. Refer to your ceramics capacitor catalog for the RMS current ratings. Multiphase operation with multiple LTM4601HV devices in parallel will lower the effective input RMS ripple current due to the interleaving operation of the regulators. Application Note 77 provides a detailed explanation. Refer to Figure 2 for the input capacitor ripple current requirement as a function of the number of phases. The figure provides a ratio of RMS ripple current to DC load current as function of duty cycle and the number of paralleled phases. Pick
RMS INPUT RIPPLE CURRENT DC LOAD CURRENT
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the corresponding duty cycle and the number of phases to arrive at the correct ripple current value. For example, the 2-phase parallel LTM4601HV design provides 24A at 2.5V output from a 12V input. The duty cycle is DC = 2.5V/12V = 0.21. The 2-phase curve has a ratio of ~0.25 for a duty cycle of 0.21. This 0.25 ratio of RMS ripple current to a DC load current of 24A equals ~6A of input RMS ripple current for the external input capacitors. Output Capacitors The LTM4601HV is designed for low output voltage ripple. The bulk output capacitors defined as COUT are chosen with low enough effective series resistance (ESR) to meet the output voltage ripple and transient requirements. COUT can be a low ESR tantalum capacitor, a low ESR polymer capacitor or a ceramic capacitor. The typical capacitance is 200F if all ceramic output capacitors are used. Additional output filtering may be required by the system designer, if further reduction of output ripple or dynamic transient spike is required. Table 2 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 5A/s transient. The table optimizes total equivalent ESR and total bulk capacitance to maximize transient performance.
0.6 0.5 0.4 0.3 0.2 0.1 0 1-PHASE 2-PHASE 3-PHASE 4-PHASE 6-PHASE 12-PHASE 0.1 0.2 0.3 0.4 0.5 0.6 0.7 DUTY FACTOR (VOUT/VIN) 0.8 0.9
4601HV F02
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Figure 2. Normalized Input RMS Ripple Current vs Duty Factor for One to Six Modules (Phases)
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LTM4601HV APPLICATIO S I FOR ATIO
Multiphase operation with multiple LTM4601HV devices in parallel will lower the effective output ripple current due to the interleaving operation of the regulators. For example, each LTM4601HV's inductor current of a 12V to 2.5V multiphase design can be read from the Inductor Ripple Current versus Duty Cycle graph (Figure 3). The large ripple current at low duty cycle and high output voltage
12 2.5V OUTPUT 10 8 IL (A) 6 4 2 0 0 20 40 60 DUTY CYCLE (VOUT/VIN) 80
4601HV F03
5V OUTPUT 1.8V OUTPUT 1.5V OUTPUT 1.2V OUTPUT 3.3V OUTPUT WITH 130k ADDED FROM VOUT TO fSET 5V OUTPUT WITH 100k ADDED FROM fSET TO GND
Figure 3. Inductor Ripple Current vs Duty Cycle
1.00 0.95 0.90 0.85 0.80 PEAK-TO-PEAK OUTPUT RIPPLE CURRENT DIr 0.75 0.70 0.65 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0
RATIO =
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 DUTY CYCLE (VO/VIN)
4601HV F04
Figure 4. Normalized Output Ripple Current vs Duty Cycle, Dlr = VOT/LI, Dlr = Each Phase's Inductor Current
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can be reduced by adding an external resistor from fSET to ground which increases the frequency. If the duty cycle is DC = 2.5V/12V = 0.21, the inductor ripple current for 2.5V output at 21% duty cycle is ~6A in Figure 3. Figure 4 provides a ratio of peak-to-peak output ripple current to the inductor current as a function of duty cycle and the number of paralleled phases. Pick the corresponding duty cycle and the number of phases to arrive at the correct output ripple current ratio value. If a 2-phase operation is chosen at a duty cycle of 21%, then 0.6 is the ratio. This 0.6 ratio of output ripple current to inductor ripple of 6A equals 3.6A of effective output ripple current. Refer to Application Note 77 for a detailed explanation of output ripple current reduction as a function of paralleled phases. The output voltage ripple has two components that are related to the amount of bulk capacitance and effective series resistance (ESR) of the output bulk capacitance. Therefore, the output voltage ripple can be calculated with the known effective output ripple current. The equation: VOUT(P-P) (IL/(8 * f * m * COUT) + ESR * IL), where
1-PHASE 2-PHASE 3-PHASE 4-PHASE 6-PHASE
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LTM4601HV APPLICATIO S I FOR ATIO
f is frequency and m is the number of parallel phases. This calculation process can be easily fulfilled using our Excel tool (Refer to the Linear Technology Module Power Design Tool). Fault Conditions: Current Limit and Overcurrent Foldback LTM4601HV has a current mode controller, which inherently limits the cycle-by-cycle inductor current not only in steady-state operation, but also in transient. To further limit current in the event of an overload condition, the LTM4601HV provides foldback current limiting. If the output voltage falls by more than 50%, then the maximum output current is progressively lowered to about one sixth of its full current limit value. Soft-Start and Tracking The TRACK/SS pin provides a means to either soft-start the regulator or track it to a different power supply. A capacitor on this pin will program the ramp rate of the output voltage. A 1.5A current source will charge up the external soft-start capacitor to 80% of the 0.6V internal voltage reference minus any margin delta. This will control the ramp of the internal reference and the output voltage. The total soft-start time can be calculated as: t SOFTSTART = 0.8 V * 0.6 V - VOUT(MARGIN) *
CIN
(
)
When the RUN pin falls below 1.5V, then the SS pin is reset to allow for proper soft-start control when the regulator is enabled again. Current foldback and force continuous mode are disabled during the soft-start process. The soft-start function can also be used to control the output ramp up time, so that another regulator can be easily tracked to it. Output Voltage Tracking Output voltage tracking can be programmed externally using the TRACK/SS pin. The output can be tracked up and
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down with another regulator. The master regulator's output is divided down with an external resistor divider that is the same as the slave regulator's feedback divider. Figure 5 shows an example of coincident tracking. Ratiometric modes of tracking can be achieved by selecting different resistor values to change the output tracking ratio. The master output must be greater than the slave output for the tracking to work. Figure 6 shows the coincident output tracking characteristics.
MASTER OUTPUT TRACK CONTROL R2 60.4k R1 40.2k SLAVE OUTPUT COUT VIN 100k VIN PGOOD MPGM RUN COMP INTVCC DRVCC PLLIN TRACK/SS VOUT VFB MARG0 MARG1 VOUT_LCL DIFFVOUT VOSNS+ VOSNS- fSET RSET 40.2k
4601HV F05
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60.4k FROM VOUT TO VFB
LTM4601HV
SGND
PGND
Figure 5
CSS 1.5A
MASTER OUTPUT
SLAVE OUTPUT OUTPUT VOLTAGE
TIME
4601HV F06
Figure 6
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LTM4601HV APPLICATIO S I FOR ATIO
Run Enable The RUN pin is used to enable the power module. The pin has an internal 5.1V zener to ground. The pin can be driven with a logic input not to exceed 5V. The RUN pin can also be used as an undervoltage lock out (UVLO) function by connecting a resistor divider from the input supply to the RUN pin: VUVLO = R1+ R2 * 1.5V R2
Power Good The PGOOD pin is an open-drain pin that can be used to monitor valid output voltage regulation. This pin monitors a 10% window around the regulation point and tracks with margining. COMP Pin This pin is the external compensation pin. The module has already been internally compensated for most output voltages. Table 2 is provided for most application requirements. A spice model will be provided for other control loop optimization. PLLIN The power module has a phase-locked loop comprised of an internal voltage controlled oscillator and a phase detector. This allows the internal top MOSFET turn-on to be locked to the rising edge of the external clock. The frequency range is 30% around the operating frequency of 850kHz. A pulse detection circuit is used to detect a clock on the PLLIN pin to turn on the phase lock loop. The pulse width of the clock has to be at least 400ns and 2V in amplitude. During the start-up of the regulator, the phase-lock loop function is disabled. INTVCC and DRVCC Connection An internal low dropout regulator produces an internal 5V supply that powers the control circuitry and DRVCC for driving the internal power MOSFETs. Therefore, if the system does not have a 5V power rail, the LTM4601HV can be directly powered by VIN. The gate driver current
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through the LDO is about 20mA. The internal LDO power dissipation can be calculated as: PLDO_LOSS = 20mA * (VIN - 5V) The LTM4601HV also provides the external gate driver voltage pin DRVCC. If there is a 5V rail in the system, it is recommended to connect DRVCC pin to the external 5V rail. This is especially true for higher input voltages. Do not apply more than 6V to the DRVCC pin. A 5V output can be used to power the DRVCC pin with an external circuit as shown in Figure 18. Parallel Operation of the Module The LTM4601HV device is an inherently current mode controlled device. Parallel modules will have very good current sharing. This will balance the thermals on the design. Figure 21 shows a schematic of the parallel design. The voltage feedback equation changes with the variable n as modules are paralleled: 60.4k + RFB n VOUT = 0.6 V RFB n is the number of paralleled modules. Figure 21 shows two LTM4601HV modules used in a parallel design. An LTM4601HV device can be used without the diff amp. Thermal Considerations and Output Current Derating The power loss curves in Figures 7 and 8 can be used in coordination with the load current derating curves in Figures 9 to 16 for calculating an approximate JA for the module with various heat sinking methods. Thermal models are derived from several temperature measurements at the bench and thermal modeling analysis. Thermal Application Note 103 provides a detailed explanation of the analysis for the thermal models and the derating curves. Tables 3 and 4 provide a summary of the equivalent JA for the noted conditions. These equivalent JA parameters are correlated to the measured values, and are improved with air flow. The case temperature is maintained at 100C or below for the derating curves. The maximum case temperature of 100C is to allow for a rise of about 13C
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LTM4601HV APPLICATIO S I FOR ATIO
5.0 4.5 4.0 POWER LOSS (W) POWER LOSS (W) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 2 6 8 4 OUTPUT CURRENT (A) 10 12 0 0 2 4 6 8 OUTPUT CURRENT (A) 10 12 5V LOSS 1 12V LOSS 24V LOSS 5 4 24V LOSS 3 12V LOSS 2
4601HV F07
Figure 7. 24VIN and 1.5V Power Loss
12 MAXIMUM LOAD CURRENT (A) 10 8 6 4 2 0 50 5VIN, 1.5VOUT 0LFM 5VIN, 1.5VOUT 200LFM 5VIN, 1.5VOUT 400LFM 60 70 80 90 AMBIENT TEMPERATURE (C) 100
4601HV F09
MAXIMUM LOAD CURRENT (A)
Figure 9. No Heat Sink 5VIN
12 MAXIMUM LOAD CURRENT (A) 10 8 6 4 2 0 50 12VIN, 1.5VOUT 0LFM 12VIN, 1.5VOUT 200LFM 12VIN, 1.5VOUT 400LFM 60 70 80 90 AMBIENT TEMPERATURE (C) 100
4601HV F11
MAXIMUM LOAD CURRENT (A)
Figure 11. No Heat Sink 12VIN
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4601HV F08
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Figure 8. 24VIN and 3.3V Power Loss
12 10 8 6 4 2 0 50 5VIN, 1.5VOUT 0LFM 5VIN, 1.5VOUT 200LFM 5VIN, 1.5VOUT 400LFM 60 70 80 90 AMBIENT TEMPERATURE (C) 100
4601HV F10
Figure 10. BGA Heat Sink 5VIN
12 10 8 6 4 2 0 50 12VIN, 1.5VOUT 0LFM 12VIN, 1.5VOUT 200LFM 12VIN, 1.5VOUT 400LFM 60 70 80 90 AMBIENT TEMPERATURE (C) 100
4601HV F12
Figure 12. BGA Heat Sink 12VIN
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LTM4601HV APPLICATIO S I FOR ATIO
12 10 8 6 4 2 0 40 60 80 AMBIENT TEMPERATURE (C) 100
4601HV F13
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
0LFM 200LFM 400LFM
Figure 13. 12VIN, 3.3VOUT, No Heat Sink
12 MAXIMUM LOAD CURRENT (A) 10 8 6 4 2 0 40 24VIN, 1.5VOUT 0LFM 24VIN, 1.5VOUT 200LFM 24VIN, 1.5VOUT 400LFM 60 80 AMBIENT TEMPERATURE (C) 100
4601HV F15
MAXIMUM LOAD CURRENT (A)
Figure 15. 24VIN, 1.5VOUT, No Heat Sink
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12 10 8 6 4 2 0 40 60 80 AMBIENT TEMPERATURE (C) 100
4601HV F14
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0LFM 200LFM 400LFM
Figure 14. 12VIN, 3.3VOUT, BGA Heat Sink
12 10 8 6 4 2 0 40 24VIN, 1.5VOUT 0LFM 24VIN, 1.5VOUT 200LFM 24VIN, 1.5VOUT 400LFM 60 80 AMBIENT TEMPERATURE (C) 100
4601HV F16
Figure 16. 24VIN, 1.5VOUT, BGA Heat Sink
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LTM4601HV APPLICATIO S I FOR ATIO
TYPICAL MEASURED VALUES COUT1 VENDORS TDK TAIYO YUDEN TAIYO YUDEN VOUT (V) 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 5 5 CIN (CERAMIC) 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V
Table 2. Output Voltage Response Versus Component Matrix (Refer to Figure 20), 0A to 6A Load Step
PART NUMBER C4532X5R0J107MZ (100UF,6.3V) JMK432BJ107MU-T ( 100F, 6.3V) JMK316BJ226ML-T501 ( 22F, 6.3V) COUT1 (CERAMIC) 3 x 22F 6.3V 1 x 100F 6.3V 2 x 100F 6.3V 4 x 100F 6.3V 3 x 22F 6.3V 1 x 100F 6.3V 2 x 100F 6.3V 4 x 100F 6.3V 3 x 22F 6.3V 1 x 100F 6.3V 2 x 100F 6.3V 4 x 100F 6.3V 3 x 22F 6.3V 1 x 100F 6.3V 2 x 100F 6.3V 4 x 100F 6.3V 3 x 22F 6.3V 1 x 100F 6.3V 2 x 100F 6.3V 4 x 100F 6.3V 3 x 22F 6.3V 1 x 100F 6.3V 2 x 100F 6.3V 4 x 100F 6.3V 1 x 100F 6.3V 2 x 100F 6.3V 3 x 22F 6.3V 4 x 100F 6.3V 1 x 100F 6.3V 3 x 22F 6.3V 2 x 100F 6.3V 4 x 100F 6.3V 2 x 100F 6.3V 1 x 100F 6.3V 3 x 22F 6.3V 4 x 100F 6.3V 1 x 100F 6.3V 3 x 22F 6.3V 2 x 100F 6.3V 4 x 100F 6.3V 4 x 100F 6.3V 4 x 100F 6.3V COUT2 (BULK) 470F 4V 470F 2.5V 330F 6.3V NONE 470F 4V 470F 2.5V 330F 6.3V NONE 470F 4V 470F 2.5V 330F 6.3V NONE 470F 4V 470F 2.5V 330F 6.3V NONE 470F 4V 470F 2.5V 330F 6.3V NONE 470F 4V 470F 2.5V 330F 6.3V NONE 470F 4V 330F 6.3V 470F 4V NONE 470F 4V 470F 4V 330F 6.3V NONE 330F 6.3V 470F 4V 470F 4V NONE 470F 4V 470F 4V 330F 6.3V NONE NONE NONE COUT2 VENDORS SANYO POSCAP SANYO POSCAP SANYO POSCAP VIN (V) 5 5 5 5 12 12 12 12 5 5 5 5 12 12 12 12 5 5 5 5 12 12 12 12 5 5 5 5 12 12 12 12 7 7 7 7 12 12 12 12 15 20 DROOP (mV) 70 35 70 40 70 35 70 49 48 54 44 61 48 54 44 54 48 44 68 65 60 60 68 65 48 56 57 60 48 51 56 70 120 110 110 114 110 110 110 114 188 159 PART NUMBER 6TPE330MIL (330F, 6.3V) 2R5TPE470M9 (470F, 2.5V) 4TPE470MCL (470F, 4V) PEAK TO PEAK (mV) 140 70 140 93 140 70 140 98 100 109 84 118 100 109 89 108 100 90 140 130 120 120 140 130 103 113 116 115 103 102 113 140 240 214 214 230 214 214 214 230 375 320 RECOVERY TIME (s) 30 20 20 30 30 20 20 20 35 30 30 30 35 30 25 25 30 20 30 30 30 30 30 20 30 30 30 25 30 30 30 25 30 30 30 30 30 35 35 30 25 25 LOAD STEP (A/s) 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 RSET (k) 60.4 60.4 60.4 60.4 60.4 60.4 60.4 60.4 40.2 40.2 40.2 40.2 40.2 40.2 40.2 40.2 30.1 30.1 30.1 30.1 30.1 30.1 30.1 30.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 13.3 13.3 13.3 13.3 13.3 13.3 13.3 13.3 8.25 8.25
CIN (BULK) 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V
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CCOMP NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE C3 47pF 100pF 22pF 100pF 100pF 100pF 22pF 100pF 100pF 33pF 100pF 100pF 100pF 33pF 100pF 100pF 47pF 100pF 100pF 100pF 100pF 100pF 100pF 100pF 100pF 220pF NONE 100pF 100pF NONE 220pF 220pF 100pF 100pF 100pF 100pF 100pF 150pF 100pF 100pF 22pF 22pF
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LTM4601HV APPLICATIO S I FOR ATIO
Table 3. 1.5V Output at 12A
DERATING CURVE Figures 9, 11, 15 Figures 9, 11, 15 Figures 9, 11, 15 Figures 10, 12, 16 Figures 10, 12, 16 Figures 10, 12, 16 VIN (V) 5, 12, 24 5, 12, 24 5, 12, 24 5, 12, 24 5, 12, 24 5, 12, 24 POWER LOSS CURVE Figure 7 Figure 7 Figure 7 Figure 7 Figure 7 Figure 7 AIR FLOW (LFM) 0 200 400 0 200 400 HEAT SINK None None None BGA Heat Sink BGA Heat Sink BGA Heat Sink JA (C/W) 15.2 14 12 13.9 11.3 10.25
Table 4. 3.3V Output at 12A
DERATING CURVE Figure 13 Figure 13 Figure 13 Figure 14 Figure 14 Figure 14 VIN (V) 12 12 12 12 12 12 POWER LOSS CURVE Figure 8 Figure 8 Figure 8 Figure 8 Figure 8 Figure 8 AIR FLOW (LFM) 0 200 400 0 200 400 HEAT SINK None None None BGA Heat Sink BGA Heat Sink BGA Heat Sink JA (C/W) 15.2 14.6 13.4 13.9 11.1 10.5
Heat Sink Manufacturer
Wakefield Engineering Part No: 20069 Phone: 603-635-2800
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LTM4601HV APPLICATIO S I FOR ATIO
to 25C inside the Module with a thermal resistance JC from junction to case between 6C/W to 9C/W. This will maintain the maximum junction temperature inside the Module below 125C. Safety Considerations The LTM4601HV modules do not provide isolation from VIN to VOUT. There is no internal fuse. If required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. Layout Checklist/Example The high integration of LTM4601HV makes the PCB board layout very simple and easy. However, to optimize its electrical and thermal performance, some layout considerations are still necessary. * Use large PCB copper areas for high current path, including VIN, PGND and VOUT. It helps to minimize the PCB conduction loss and thermal stress.
VIN CIN CIN
GND
COUT VOUT
COUT
Figure 17. Recommended Layout
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* Place high frequency ceramic input and output capacitors next to the VIN, PGND and VOUT pins to minimize high frequency noise. * Place a dedicated power ground layer underneath the unit. Refer frequency synchronization source to power ground. * To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. * Do not put vias directly on pads unless they are capped. * Use a separated SGND ground copper area for components connected to signal pins. Connect the SGND to PGND underneath the unit. Figure 17 gives a good example of the recommended layout.
SIGNAL GND
4601HV F17
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LTM4601HV APPLICATIO S I FOR ATIO
Frequency Adjustment The LTM4601HV is designed to typically operate at 850kHz across most input conditions. The fSET pin is normally left open or decoupled with an optional 1000pF capacitor. The switching frequency has been optimized for maintaining constant output ripple noise over most operating ranges. The 850kHz switching frequency and the 400ns minimum off time can limit operation at higher duty cycles like 5V to 3.3V, and produce excessive inductor ripple currents for lower duty cycle applications like 28V to 5V. The 5V and 3.3V drop out curves are modified by adding an external resistor on the fSET pin to allow for lower input voltage operation, or higher input voltage operation. Example for 5V Output LTM4601HV minimum on-time = 100ns; tON = ((4.8 * 10pf)/IfSET) LTM4601HV minimum off-time = 400ns; tOFF = t - tON, where t = 1/Frequency Duty Cycle = tON/t or VOUT/VIN Equations for setting frequency: IfSET = (VIN/(3 * RfSET)), for 28V operation, ISET = 238A, tON = ((4.8 * 10pF)/IfSET), tON = 202ns, where the internal RfSET is 39.2k. Frequency = (VOUT/(VIN * tON)) = (5V/(28 * 202ns)) ~ 884kHz. The inductor ripple current begins to get high at the higher input voltages due to a larger voltage across the inductor. This is noted in the Typical Inductor Ripple Current verses Duty Cycle graph (Figure 3) where IL 10A at 20% duty cycle. The inductor ripple current can be lowered at the higher input voltages by adding an external resistor from fSET to ground to increase the switching frequency. A 7A ripple current is chosen, and the total peak current is equal to 1/2 of the 7A ripple current plus the output current. The 5V output current is limited to 8A, so the total peak current is less than 11.5A. This is below
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the 14A peak specified value. A 100k resistor is placed from fSET to ground, and the parallel combination of 100k and 39.2k equates to 28k. The IfSET calculation with 28k and 28V input voltage equals 333A. This equates to a tON of 144ns. This will increase the switching frequency from ~884kHz to ~1.24MHz for the 28V to 5V conversion. The minimum on time is above 100ns at 28V input. Since the switching frequency is approximately constant over input and output conditions, then the lower input voltage range is limited to 10V for the 1.24MHz operation due to the 400ns minimum off time. Equation: tON = (VOUT/VIN) * (1/Frequency) equates to a 400ns on time, and a 400ns off time. The "VIN to VOUT Step Ratio Curve" reflects an operating range of 10V to 28V for 1.24MHz operation with a 100k resistor to ground as shown in Figure 18, and an 8V to 16V operation for fSET floating. These modifications are made to provide wider input voltage ranges for the 5V output designs while limiting the inductor ripple current, and maintaining the 400ns minimum off time. Example for 3.3V Output LTM4601HV minimum on-time = 100ns; tON = ((3.3 * 10pF)/IfSET) LTM4601HV minimum off-time = 400ns; tOFF = t - tON, where t = 1/Frequency Duty Cycle (DC) = tON/t or VOUT/VIN Equations for setting frequency: IfSET = (VIN/(3 * RfSET)), for 28V operation, IfSET = 238A, tON = ((3.3 * 10pf)/IfSET), tON = 138.7ns, where the internal RfSET is 39.2k. Frequency = (VOUT/(VIN * tON)) = (3.3V/(28 * 138.7ns)) ~ 850kHz. The minimum on-time and minimumoff time are within specification at 139ns and 1037ns. The 4.5V minimum input for converting 3.3V output will not meet the minimum off-time specification of 400ns. tON = 868ns, Frequency = 850kHz, tOFF = 315ns.
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LTM4601HV APPLICATIO S I FOR ATIO
Solution Lower the switching frequency at lower input voltages to allow for higher duty cycles, and meet the 400ns minimum off-time at 4.5V input voltage. The off-time should be about 500ns with 100ns guard band. The duty cycle for (3.3V/4.5) = ~73%. Frequency = (1 - DC)/tOFF, or (1 - 0.73)/500ns = 540kHz. The switching frequency needs to be lowered to 540kHz at 4.5V input. tON = DC/ frequency, or 1.35s. The fSET pin voltage compliance is 1/3 of VIN, and the IfSET current equates to 38A with the internal 39.2k. The IfSET current needs to be 24A for
VOUT VIN 10V TO 28V R2 100k R4 100k
VIN PGOOD MPGM RUN COMP INTVCC DRVCC
LTM4601HV
5% MARGIN C2 10F 25V R1 392k 1% C1 10F 25V
SGND
IMPROVE EFFICIENCY FOR 12V INPUT DUAL CMSSH-3C3
SOT-323
Figure 18. 5V at 8A Design Without Differential Amplifier
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540kHz operation. As shown in Figure 19, a resistor can be placed from VOUT to fSET to lower the effective IfSET current out of the fSET pin to 24A. The fSET pin is 4.5V/3 =1.5V and VOUT = 3.3V, therefore 130k will source 14A into the fSET node and lower the IfSET current to 24A. This enables the 540kHz operation and the 4.5V to 28V input operation for down converting to 3.3V output. The frequency will scale from 540kHz to 1.1 MHz over this input range. This provides for an effective output current of 8A over the input range.
TRACK/SS CONTROL PLLIN TRACK/SS VOUT VFB MARG0 MARG1 VOUT_LCL DIFFVOUT VOSNS+ VOSNS- fSET RfSET 100k MARGIN CONTROL RSET 8.25k REVIEW TEMPERATURE DERATING CURVE
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C3 100F 6.3V SANYO POSCAP
VOUT 5V 8A 22F 6.3V REFER TO TABLE 2
PGND
4601HV F18
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LTM4601HV APPLICATIO S I FOR ATIO
VOUT VIN 4.5V TO 16V R2 100k R4 100k
VIN PGOOD MPGM RUN COMP INTVCC DRVCC
PGOOD
C2 10F 25V x3
R1 392k SGND PGND
5% MARGIN
Figure 19. 3.3V at 10A Design
VOUT VIN 22V TO 28V R2 100k R4 100k
VIN PGOOD
PGOOD
CIN BULK OPT
+
CIN 10F 25V x3 CER
MPGM RUN ON/OFF COMP INTVCC DRVCC R1 392k SGND
5% MARGIN
Figure 20. Typical 22V to 28V, 1.5V at 10A Design, 500kHz
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TRACK/SS CONTROL PLLIN TRACK/SS VOUT VFB MARG0 MARG1 VOUT_LCL DIFFVOUT VOSNS+ VOSNS- fSET RfSET 130k RSET 13.3k REVIEW TEMPERATURE DERATING CURVE VOUT 3.3V 10A C3 100F 6.3V SANYO POSCAP 22F 6.3V LTM4601HV
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MARGIN CONTROL
4601HV F19
CLOCK SYNC C5 0.01F PLLIN TRACK/SS VOUT VFB MARG0 MARG1 VOUT_LCL DIFFVOUT VOSNS+ VOSNS- fSET RfSET 175k VIN
4601HV F20
REVIEW TEMPERATURE DERATING CURVE C3 100pF MARGIN CONTROL COUT1 100F 6.3V
+
COUT2 470F 6.3V
VOUT 1.5V 10A
LTM4601HV
PGND
RSET 40.2k
REFER TO TABLE 2 FOR DIFFERENT OUTPUT VOLTAGE
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LTM4601HV APPLICATIO S I FOR ATIO
VOUT VIN 6V TO 28V CLOCK SYNC 0 PHASE R2 100k R4 100k VIN PGOOD MPGM RUN COMP INTVCC DRVCC PLLIN TRACK/SS VOUT VFB MARG0 MARG1 VOUT_LCL DIFFVOUT VOSNS+ VOSNS- fSET RSET 6.65k TRACK/SS CONTROL
+
C1 0.1F 118k 1% 1 2 3 LTC6908-1 V+ GND SET OUT1 OUT2 MOD 6 5 4
C5* 100F 25V C2 10F 25V x2
2-PHASE OSCILLATOR
PGOOD C8 10F 25V x2
*C5 OPTIONAL TO REDUCE ANY LC RINGING. NOT NEEDED FOR LOW INDUCTANCE PLANE CONNECTION
Figure 21. 2-Phase Parallel, 3.3V at 20A Design
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60.4k + R SET N RSET N = NUMBER OF PHASES VOUT = 0.6V VOUT 3.3V 20A C6 220pF LTM4601HV C3 22F 6.3V C4 470F 6.3V
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R1 392k
REFER TO TABLE 2 100pF
SGND
PGND
5% MARGIN
MARGIN CONTROL
CLOCK SYNC 180 PHASE TRACK/SS CONTROL C7 0.033F
VIN PGOOD MPGM RUN COMP INTVCC DRVCC 392k SGND
PLLIN TRACK/SS VOUT VFB MARG0 MARG1 VOUT_LCL DIFFVOUT VOSNS+ VOSNS- fSET C3 22F 6.3V
+
C4 470F 6.3V
LTM4601HV
REFER TO TABLE 2
PGND
4601HV F21
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LTM4601HV TYPICAL APPLICATIO S
LTC6908-1 2-PHASE OSCILLATOR V+ R1 118k 3.3V VIN 6V TO 28V R3 100k R4 100k C8 0.1F GND SET 0 PHASE OUT1 OUT2 MOD 180 PHASE
VIN
PLLIN C2 100F 6.3V
C1 10F 35V R2 392k C3 0.15F
PGOOD VOUT RUN FB COMP VOUT_LCL DIFFVOUT INTVCC LTM4601HV DRVCC VOSNS+ MPGM VOSNS- MARG0 fSET TRACK/SS MARG1 SGND PGND
LTC6908-1 2-PHASE OSCILLATOR V+ R1 182k 3.3V VIN 6V TO 28V R3 100k R4 100k C8 0.1F GND SET 0 PHASE OUT1 OUT2 MOD 180 PHASE
VIN
PLLIN C8 47pF R1 30.1k C2 100F 6.3V
C1 10F 35V R2 392k C3 0.15F
PGOOD VOUT RUN FB COMP VOUT_LCL DIFFVOUT INTVCC LTM4601HV DRVCC VOSNS+ MPGM VOSNS- MARG0 fSET TRACK/SS MARG1 SGND PGND
24
U
3.3V R7 100k R8 100k
R1 13.3k
VOUT1 3.3V C4 10A 150F 6.3V 3.3V TRACK R16 60.4k R15 19.1k
VIN
PLLIN C6 100F 6.3V
C5 10F 35V R6 392k
MARGIN CONTROL
PGOOD VOUT RUN FB COMP VOUT_LCL DIFFVOUT INTVCC LTM4601HV DRVCC VOSNS+ MPGM VOSNS- MARG0 fSET TRACK/SS MARG1 SGND PGND
R5 19.1k
VOUT2 2.5V C7 10A 150F 6.3V
MARGIN CONTROL
4601HV F22
Figure 22. Dual Outputs (3.3V and 2.5V) with Tracking
3.3V VOUT1 1.8V C4 10A 220F 6.3V R7 100k R8 100k VOUT2 1.5V C7 10A 220F 6.3V
VIN
PLLIN
MARGIN CONTROL
3.3V TRACK R16 60.4k R15 40.2k
C5 10F 35V R6 392k
PGOOD VOUT RUN FB COMP VOUT_LCL DIFFVOUT INTVCC LTM4601HV DRVCC VOSNS+ MPGM VOSNS- MARG0 fSET TRACK/SS MARG1 SGND PGND
C9 47pF R5 40.2k
C6 100F 6.3V
MARGIN CONTROL
4601HV F23
Figure 23. Dual Outputs (1.8V and 1.5V) with Tracking
4601hvf
LGA Package 118-Lead (15mm x 15mm)
(Reference LTM DWG # 05-05-1801, Rev O)
6.9850
5.7150
4.4450
3.1750
1.9050
0.6350 0.0000 0.6350
1.9050
3.1750
4.4450
5.7150
6.9850
2.72 - 2.92 Y
aaa Z 15 BSC X
6.9850 PAD 1 CORNER 4
5.7150
4.4450
3.1750
PACKAGE DESCRIPTIO
1.9050 15 BSC SUBSTRATE
0.6350 0.0000 0.6350 MOLD CAP
1.9050 0.27 - 0.37 2.45 - 2.55 DETAIL B bbb Z Z
3.1750
4.4450
5.7150
6.9850
aaa Z
SUGGESTED SOLDER PAD LAYOUT TOP VIEW
DETAIL A DETAIL B 0.60 - 0.66 M L K J H G F E D C B PADS SEE NOTES 3 A 7 8 9 10 11 12 DETAIL A 0.60 - 0.66 eee M X Y
TOP VIEW
0.12 - 0.28
13.97 BSC
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS 3 4 LAND DESIGNATION PER JESD MO-222, SPP-010 DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. THE TOTAL NUMBER OF PADS: 118 SYMBOL TOLERANCE 0.10 aaa 0.10 bbb 0.03 eee
13.97 BSC
1.27 BSC
LGA 118 0306 REV O
C(0.30) PAD 1
1
2
3
4
5
6
BOTTOM VIEW
U LTM4601HV
25
4601hvf
LTM4601HV PACKAGE DESCRIPTIO
PIN NAME A1 VIN A2 VIN A3 VIN A4 VIN A5 VIN A6 VIN A7 INTVCC A8 PLLIN A9 TRACK/SS A10 RUN A11 COMP A12 MPGM PIN NAME G1 PGND G2 PGND G3 PGND G4 PGND G5 PGND G6 PGND G7 PGND G8 PGND G9 PGND G10 G11 G12 PGOOD
26
U
Pin Assignment Tables (Arranged by Pin Number)
PIN NAME B1 VIN B2 VIN B3 VIN B4 VIN B5 VIN B6 VIN B7 B8 B9 B10 B11 B12 fSET PIN NAME H1 PGND H2 PGND H3 PGND H4 PGND H5 PGND H6 PGND H7 PGND H8 PGND H9 PGND H10 H11 H12 SGND PIN NAME C1 VIN C2 VIN C3 VIN C4 VIN C5 VIN C6 VIN C7 C8 C9 C10 C11 C12 MARG0 PIN NAME J1 VOUT J2 VOUT J3 VOUT J4 VOUT J5 VOUT J6 VOUT J7 VOUT J8 VOUT J9 VOUT J10 VOUT J11 J12 VOSNS+ PIN NAME D1 PGND D2 PGND D3 PGND D4 PGND D5 PGND D6 PGND D7 D8 D9 D10 D11 D12 MARG1 PIN NAME K1 VOUT K2 VOUT K3 VOUT K4 VOUT K5 VOUT K6 VOUT K7 VOUT K8 VOUT K9 VOUT K10 VOUT K11 VOUT K12 DIFFVOUT PIN NAME E1 PGND E2 PGND E3 PGND E4 PGND E5 PGND E6 PGND E7 PGND E8 E9 E10 E11 E12 DRVCC PIN NAME L1 VOUT L2 VOUT L3 VOUT L4 VOUT L5 VOUT L6 VOUT L7 VOUT L8 VOUT L9 VOUT L10 VOUT L11 VOUT L12 VOUT_LCL PIN NAME F1 PGND F2 PGND F3 PGND F4 PGND F5 PGND F6 PGND F7 PGND F8 PGND F9 PGND F10 F11 F12 VFB PIN NAME M1 VOUT M2 VOUT M3 VOUT M4 VOUT M5 VOUT M6 VOUT M7 VOUT M8 VOUT M9 VOUT M10 VOUT M11 VOUT M12 VOSNS-
4601hvf
LTM4601HV PACKAGE DESCRIPTIO
PIN NAME A1 A2 A3 A4 A5 A6 B1 B2 B3 B4 B5 B6 C1 C2 C3 C4 C5 C6 VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN D1 D2 D3 D4 D5 D6 E1 E2 E3 E4 E5 E6 E7 F1 F2 F3 F4 F5 F6 F7 F8 F9 G1 G2 G3 G4 G5 G6 G7 G8 G9 H1 H2 H3 H4 H5 H6 H7 H8 H9
PIN NAME PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
Pin Assignment Tables (Arranged by Pin Function)
PIN NAME VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT A7 A8 A9 A10 A11 A12 B12 C12 D12 E12 F12 G12 H12 J12 K12 L12 M12 PIN NAME INTVCC PLLIN TRACK/SS RUN COMP MPGM fSET MARG0 MARG1 DRVCC VFB PGOOD SGND VOSNS+ DIFFVOUT VOUT_LCL VOSNS- B7 B8 B9 B10 B11 C7 C8 C9 C10 C11 D7 D8 D9 D10 D11 E8 E9 E10 E11 F10 F11 G10 G11 H10 H11 J11 PIN NAME 4601hvf
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LTM4601HV RELATED PARTS
PART NUMBER LTC2900 LTC2923 LT3825/LT3837 LTM4600 LTM46O2 LTM4603 DESCRIPTION Quad Supply Monitor with Adjustable Reset Timer Power Supply Tracking Controller Synchronous Isolated Flyback Controllers 10A DC/DC Module 6A DC/DC Module 6A DC/DC Module with Tracking PLL/Margining COMMENTS Monitors Four Supplies; Adjustable Reset Timer Tracks Both Up and Down; Power Supply Sequencing No Optocoupler Required; 3.3V, 12A Output; Simple Design Fast Transient Response Pin Compatible with the LTM4600 Pin Compatible with the LTM4601
This product contains technology licensed from Silicon Semiconductor Corporation.
(R)
4601hvf LT 0307 * PRINTED IN USA
28
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2007

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